Host-daughtercard configuration with double data rate bus

ABSTRACT

A double data rate bus system includes a host-network interface card configuration wherein the host is configured to recognize the network interface card to establish a double data rate bus between the host and the network interface card. The host is configured to generate a plurality of generic data frame queues. Each of the generic data frame queues is configured to receive and to transmit generic data frames via the double data rate bus. The network interface card is configured to transmit a plurality of dynamic memory access read requests to the host via the double data rate bus. The host is configured to allow each of the plurality of dynamic memory access read requests to remain pending prior to responding to anyone of the plurality of dynamic memory access read requests.

PRIORITY CLAIM

This application is a continuation application of U.S. Non-Provisionalapplication Ser. No. 12/339,732, filed Dec. 19, 2008 (now U.S. Pat. No.8,281,049). The contents of U.S. Non-Provisional application Ser. No.12/339,732 (now U.S. Pat. No. 8,281,049) are incorporated by referencein their entirety.

FIELD

The present disclosure relates generally to network interface cards.

BACKGROUND

Host platforms may communicate with corresponding networks throughnetwork interface cards. The network interface cards may be implementedas peripheral devices such as daughtercards. The daughtercards maymanage data flowing to and from the host platform. The host platform anddaughtercard may communicate with one another to indicate currentconditions pertaining to the network and the host platform. The networkand host platform may utilize the daughtercard to perform datatransactions with one another.

BRIEF DESCRIPTION OF THE DRAWINGS

The components and the figures are not necessarily to scale, emphasisinstead being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts throughout the different views.

FIG. 1 depicts a block diagram of an example data bus for ahost-daughtercard configuration.

FIG. 2 depicts a block diagram of an example host-daughtercard system.

FIG. 3 depicts a block diagram of an example daughtercard configuration.

FIG. 4 depicts a flow diagram of an example operation of performingdirect memory access transactions.

FIG. 5 depicts a flow diagram of an example operation of utilizing aplurality of generic data frame queues.

FIG. 6 depicts an example of a bus protocol used to transmit and receivedata from a plurality of generic data frame queues.

DESCRIPTION OF EXAMPLE EMBODIMENTS Overview

According to one aspect of the disclosure, a double data rate bus systemmay include a host-network interface card configuration where the hostis configured to recognize the network interface card to establish adouble data rate bus between the host and the network interface card.The host may be configured to generate a plurality of generic data framequeues. Each of the generic data frame queues is configured to receiveand to transmit generic data frames via the double data rate bus.

According to another aspect of the disclosure, the network interfacecard may be configured to transmit a plurality of dynamic memory accessread requests to the host via the double data rate bus, and where thehost is configured to allow each of the plurality of dynamic memoryaccess read requests to remain pending prior to responding to anyone ofthe plurality of dynamic memory access read requests.

According to another aspect of the disclosure, a method of operating adouble data rate bus system may include passing a first generic dataframe via a double data rate bus. The first generic data frame maycorrespond to a first generic data frame queue. The method may furtherinclude suspending the passing of the first generic data frame based ona first predetermined condition. The method may further include passinga second generic data frame via the double data rate bus upon suspensionof the passing of the first generic data frame. The second generic dataframe may correspond to a second generic data frame queue. The methodmay further include resuming the passing of the first generic data framevia the double data rate bus upon completion of transmission of thesecond generic data frame.

According to another aspect of the disclosure, a computer-readablemedium encoded with computer executable instructions that are executablewith a processor. The computer-readable medium may comprise instructionsexecutable to pass a first generic data frame via a double data ratebus. The first generic data frame may correspond to a first generic dataframe queue. The computer readable medium may further includeinstructions executable to suspend the passing of the first generic dataframe based on a first condition. The computer readable medium mayfurther include instructions to transmit a second generic data frame viathe double data rate bus upon suspension of passing the first genericdata frame. The second generic data frame may correspond to a secondgeneric data frame queue. The computer readable medium may furtherinclude instructions to resume passing the first generic data frame viathe double data rate bus upon completion of transmission of the secondgeneric data frame.

Example Embodiments

In one example, a host-network interface card arrangement may be used tocommunicate with a network, such as a wide area network. The host maycommunicate with a network through a network interface card. The networkinterface card and host may communicate with one another over a doubledata rate bus. In one example, multiple generic data frame queues may beestablished in a host allowing generic data frames to be transmitted andreceived by the generic data frame queues via the double data rate bus.In another example, the host may receive a plurality of dynamic memoryaccess read requests from the network interface card via the double datarate bus. The received plurality of dynamic memory access read requestsmay remain outstanding prior to the host responding to any of theoutstanding dynamic memory access read requests.

In one example shown in FIG. 1, a daughtercard 10 may be connected to ahost platform 14. The example shown in FIG. 1 may be used in a routingplatform, which may include any component such a router, bridge, switch,layer 2 or layer 3 switch, gateway, etc., that refers to componentsutilized to implement connectivity within a network or between networks.

The daughtercard 10 may be a plug-in module that provides a wide areanetwork (WAN) interface to any routers or routing devices that may beinterconnected to the daughtercard 10. FIG. 1 shows a block diagram ofan example system that includes a daughtercard 10 that may be referredto as an enhanced high-speed wide-area-network interface card (EHWIC)that may support an 8-bit double-data rate (DDR) bi-directional bus 12.The EHWIC 10 may communicate with a host platform 14 via the DDR bus 12.Signals depicted in FIG. 1 are: TxD[7:0]—transmit data bus from host;TxCtrl—transmit control bit from host; TxClk—transmit clock from host;RxD[7:0]: receive data bus to host; RxCtrl—receive control bit to host;and, RxClk: receive clock to host.

In one example the DDR bus 12 is a synchronous bus. The DDR bus 12 maybe used to: 1) provide a high-speed data path between the host platform14 and the EHWIC 10 for WAN data; 2) provide access to the on-boardregisters; and, 3) to provide a direct memory access (DMA) of the hostplatform 14 for the EHWIC 10 on-board devices. In one example, TxClk andRxClk may run at 50 MHz. The DDR mode allows data to be captured onevery clock edge. In one example, the DDR mode provides aggregatebandwidth of approximately 800 Mbps (400 Mbps in each direction).

In one example, address pins ADDR[7:0] of a legacy Host/WIC parallelinterface may be appropriated as the TxD[7:0] host to data bus in theDDR bus 12 of the Host/HWIC interface. Also, data pins of a data busDATA[7:0] of the legacy Host/WIC parallel interface may be appropriatedas the RXD[7:0] data bus to host in the DDR bus of the Host/HWICinterface. Additionally, an enable signal CS_(—L) of the legacyinterface may be appropriated as the TxCtrl pin of the Host/HWICinterface and a read signal RD_(—L) pin of the legacy Host/WIC interfacemay be appropriated as the RxCtrl pin of the Host/HWIC interface.Further, legacy Host/WIC parallel interface echo clock pins have beenappropriated as the TxClk and RxClk pins in the DDR bus 12 of theHost/HWIC interface.

In one example, an EHWIC interface may be plug compatible with a legacyWIC/Host interface. However, the functionality of some of the pins maydiffer in this implementation. In the presently-described example, theparallel port pins and the “Echo Clock” (TxCE) pins of the legacyHost/WIC parallel interface may be cannibalized for the EHWIC high-speedbus, the DDR bus 12. This provides for backwards compatibility by stillleaving serial peripheral bus (SPI) lines (e.g., SPI bus 30 in FIG. 3),serial communication controllers (SCC's) capable of handling multipleprotocols such as high-level data link control (HDLC), universalasynchronous receiver/transmitter (UART), asynchronous HOLC, transparentmode, or binary synchronous communication (BiSYNC), for example, andinterrupt lines, etc. available for conventional uses in the legacyHost/WIC parallel interface.

FIG. 2 is a block diagram of a host-EHWIC system. In FIG. 2 the hostplatform 14 includes host memory 16 and a central processing unit (CPU)18 coupled to a host termination logic block 20 including an EHWICinterface 22. The host termination logic 20 may include logic (forexample in the form of an field programmable gate array (FPGA) or anapplication-specific integrated circuit (ASIC)) which resides on thehost platform 14 and serves as an interface between the HWIC DDR bus 12and the rest of the devices on the motherboard.

The EHWIC 10 may include an EHWIC termination logic block 24 includingan EHWIC interface 26. The EHWIC termination logic 24 may include logic(for example in the form of an FPGA or ASIC), which resides on the EHWIC10 and serves as an interface between the DOR bus 12 and other deviceson the motherboard. The EHWIC interface 26 may be coupled to a 68-pinconnector 28, which may be pin compatible with a legacy EHWIC connector(not shown).

FIG. 3 is a block diagram of the example EHWIC interface 26 coupled tothe connector 28. The EHWIC 10 side may include a SPI bus 30 connectedto a cookie 32, which in one example may be a non-volatile memory, suchas a non-volatile RAM (NVRAM) in the form of an EEPROM, storinginformation about a particular implementation. The DDR bus 12 is coupledto the EHWIC termination logic 24 via the EHWIC interface 26, which mayinclude a power pin (not shown) for supplying power to the EHWIC 10. Inone example, the EHWIC termination logic 24 resides in a FPGA 34 havinga set of configurable registers 36. In one example, the registers 36 maybe used to configure the EHWIC 10.

One component of backward compatibility is providing the host platform14 with a system for determining whether a legacy or upgradeddaughtercard has been connected. In one example, this function may berequired because, although the parts are pin compatible, certain pinsare used to perform completely different functions. In one example, anEHWIC 10 may be plugged into an older host platform, which, in oneexample, may be the host platform 14, where the old host platform 14 maystill access the cookie 32 on the EHWIC 10 via the SPI lines 30 anddetermine that an inserted WIC, such as the EHWIC 10, is not supported.The EHWIC 10 may be required to not drive the Rx lines of the DDR bus 12until “enabled”, so that the WIC parallel port bus pins will not causebus contention in the event that an EHWIC 10 is inserted into an olderhost platform 14. Also, the legacy SCC's may still be available on anEHWIC 10 and can be used for purposes such as management channels.

Two types of frames may be used for communication between the EHWIC 10and the host platform 14 via the DDR bus 12: control frames and dataframes. Data frames may used to pass the larger packets of data betweenthe host platform 14 and the EHWIC 10, en route to and from the lineinterface. The control frames may be smaller in nature, and performadministrative functions, which may pre-empt the data frames in order toreduce latency. In one example, the control frame formats may begenerated and received in hardware, whereas the data frame formats maybe determined by the host CPU 18 (with the exception of direct memoryaccess (DMA) frames noted below.

The control bits (RxCtrl, TxCtrl) may distinguish data frames fromcontrol frames: TxCtrl, RxCtrl=“0”: indicates that streaming data isbeing passed, TxCtrl, RxCtrl=“1”: indicates that control information isbeing passed. In one example, the Tx and Rx buses may continuously betransmitting bytes, such as control bytes, data bytes, or idle bytes.

In one example the EHWIC 10 and the host platform 14 may communicatewith one another through a frame-based protocol. The frame-basedprotocol may implement at least two types of data frames, such as DMAdata frames and generic data frames (GDFs). In one example, both DMAdata frames and GDFs may be transmitted if and only if the respectivecontrol bit (TxCtrl or RxCtrl) is “0”; all data frames may carry a CRC8as the last byte; and the DMA data frames and GDFs may start with anencapsulation header. The GDFs may begin with the 0×12 byte. The DMAdata frames may begin with the 0×61, 0×62, 0×66, or 0×67.

In one example, a DMA data frame may serve as a vehicle forEHWIC-initiated DMA transactions. The DMA data frame may allow the EHWIC10 to read and write to host memory. DMA data frames may be processedentirely in hardware, so it is not necessary for a host processor, suchas the host CPU 18, to be involved in these transactions. For example,simple register accesses may be inefficient for reading blocks ofregisters so DMA frames are utilized to transfer blocks or register datafrom the EHWIC 10 to the host 14 over the DDR bus 12. The EHWIC 10requires data structures set up in host processor memory to support itsGDF transmit and receive operations. All of these data structures areshared by the host CPU 18 and the host termination logic 20 through DMAaccesses.

The GDFs may be an implementation-specific frame agreed upon betweenhost driver software and the EHWIC termination logic 24. For example, adata frame may be an internet protocol (IP) packet or asynchronoustransfer mode (ATM) cell that the EHWIC termination logic 24 sends to orreceives from a physical layer interface device for data transfer deviceon the EHWIC 10, for example. In another example, there may be anencapsulation, such as a header with an 8-bit port number indicatingwhich physical layer interface device the EHWIC termination logic 24sends/receives the packet from. One purpose of the GDF may be to allowflexibility to create whatever frame format will best suit a specificEHWIC being designed.

The DMA frames and GDFs may each be processed in a different manner. TheDMA data frames may originate in hardware (on the EHWIC 10 if it is aDMA request, or on the host if it is a DMA response). Upon receipt theyare also processed entirely in hardware, leaving the host CPU completelyuninvolved in the transaction (until perhaps the very end, after thetransaction is completed, when the host is notified via interrupt that aDMA transaction has occurred). FIG. 2 shows an example, in which theEHWIC 10 is configured to generate a plurality of DMA read requests 27individually designated as DMA read 1 through N. DMA read throughput maybe modeled by the following equation:

$\begin{matrix}{{{DMA}\mspace{14mu} {Read}\mspace{14mu} {Throughput}} = \frac{{DMATransaction}\mspace{14mu} {{Size} \cdot {DMAOutstanding}}\mspace{14mu} {Reads}}{{DMATransaction}\mspace{14mu} {Latency}}} & {{EQN}.\mspace{14mu} 1}\end{matrix}$

In one example, the plurality of DMA outstanding DMA read requests 27may be up to 8 (e.g., N may be 8 in FIG. 2), which may result in up to 8times the DMA read throughput. Thus, once a DMA read request frame isissued, the EHWIC 10 allows additional DMA read requests 27 to be issuedwhile other DMA read response(s) are still pending in the host platform14. At any point in time, an EHWIC 10 may be allowed a maximum of 8pending EHWIC DMA read responses.

DMA Outstanding Reads of Eqn. 1 may be the number of outstanding readsthat the EHWIC 10 has issued at any point in time. If a host systemreturns read responses faster than an EHWIC 10 can issue DMA readrequests 27, the EHWIC 10 will only have (at most) one outstanding readat any point in time, therefore no DMA Read Throughput increase will beafforded. Likewise if the EHWIC 10 is only fast enough to sustain acouple of outstanding reads, the DMA Read Throughput will only beincreased by that proportional amount (×2).

EHWIC DMA read responses by the host platform 14 may be required to bereturned in the order that the DMA read requests 27 are issued. If anyDMA reads requests 27 are re-ordered outside of the EHWIC hosttermination logic 24 (e.g., in a system controller), the DMA readrequests 27 must be returned to the original (request) order before theread responses are sent over the DDR bus 12.

A DMA write frame (not shown) followed by a DMA read request 27 mayoccur in a serial fashion due to the nature of the DMA Write Frame (aspreviously noted). However, the host termination logic 20 may permit aDMA write frame to immediately follow a DMA read request 27, even beforea DMA read-response frame (not shown) has been sent. The DMA readrequests 27 may be interleaved with DMA write frames in any manner andregardless of the arrival of read response frames as long as the maximumnumber of outstanding DMA read requests 27 is not exceeded. This mayallow DMA operations to more fully utilize the DDR bus 12 by offeringmaximum flexibility in the movement of DMA data across the DDR bus 12 inboth directions.

FIG. 4 shows a flowchart depicting an example operation of performingDMA transactions via a DDR bus. The operation may include an act 100 ofgenerating a plurality of DMA read requests. In one example, act 100 maybe performed with a configuration such as that shown in FIG. 2. TheEHWIC 10 may generate a plurality of DMA read requests 27. The operationmay also include an act 102 of serially transmitting the DMA readrequests via a DDR bus. In the example of FIG. 2, act 102 may beperformed by the EHWIC 10 by transmitting the DMA read requests 27 viathe DDR bus 12 to the host platform 14.

The operation may further include an act 104 of receiving each of theplurality of DMA read requests prior to generating a DMA read responsefor at least one of the DMA read requests. In the example of FIG. 2, act104 may be performed by the host platform 14 receiving each of theplurality of DMA read requests 27 prior to a DMA read responses beinggenerated by the host platform 14. In one example, the host platform 14may have up to 8 outstanding DMA read requests 27 prior to generating aDMA read response.

GDFs may be processed substantially in software on the host side. Anyspecial encapsulations for transmit frames (outside of the initial 0×12byte) must be created by the host processor. And likewise, receivedframes are also entirely processed by the host processor (after theleading 0×12 byte and trailing CRCS byte is removed (see FIG. 6)).

On the EHWIC side, GDFs may be processed in hardware (unless a processorresides on the EHWIC 10), which has carnal knowledge of theEHWIC-specific GDF, that has been agreed upon between the host CPU 18and hardware of the EHWIC 10. The flexibility of the types of dataframes is different. Since the DMA data frame is processed entirely inhardware, it is not flexible and may remain exactly the same format fromEHWIC to EHWIC.

Since the GDF is created and parsed by the host CPU 18, the format ofthe GDF is extremely flexible. It is intended that the host CPU 18 willchoose GDF that will facilitate design of each particular EHWIC 10.

In one example, the EHWIC 10 may be configured to operate with aplurality of GDF rings 29 in the host platform 14 as shown in FIG. 2.The plurality of GDF rings 29 may allow proper prioritization ofdifferent classes of service, e.g., voice, video, management, and data.The GDF rings 29 exist in both receive and transmit directions, and theGDFs 31 may include additional per queue DDR bus flow control features.In FIG. 2, the host platform 14 is shown as including the plurality ofGDF rings 29 individually denoted, as GDF rings 0 through 3, which mayeach be considered a dedicated GDF queue.

FIG. 5 shows a flowchart depicting an operation of utilizing a pluralityof GDF queues generated in a host platform. In the example configurationshown in FIG. 2, GDFs may be passed via the DDR bus 18 allowing the GDFrings 29, or queues, or transmit or receive GDFs. An act 200 may includeserially receiving or transmitting each of a plurality of GDFs via a DDRbus. In one example, act 200 may be performed using a configurationshown in FIG. 2 in which GDFs 31 may be transmitted and received by thehost platform 14. The host platform 14 may include a plurality of GDFrings 29 in the host termination logic 20. Each GDF ring 0 through 3 mayreceive and transmit a GDF via the DDR bus 12.

The operation may further include an act 202 of suspending each GDFreceipt or transmission if congestion is occurring during the respectivereceipt or transmission. For example, in FIG. 2, a GDF 31 may bereceived by the GDF ring 0. This receipt may become congested if the GDFring 0 is becoming full. This receipt may be suspended, allowing anotherGDF ring 29, such as GDF ring 1 through 3, to receive GDFs, whileexperience uncongested conditions. The suspension may occur through acontrol byte being transmitted from the host platform 14 to the EHWIC10. The suspension may occur accordingly for the other GDF rings 29.Similarly, this may occur in the transmit direction. For example, a GDF31 may be transmitted by a GDF ring 29. Transmission may need to besuspended if network congestion is occurring. The host platform 14 maybe made aware through a control byte transmitted by the EHWIC 10 via theDDR bus 12.

The operation may further include an act 204 of resuming each suspendedGDF receipt or transmission if a suspended GDF receipt/transmission isno longer congested and no other GDF receipt or transmission iscurrently occurring. For example, in FIG. 2 if a GDF 31 receipt ortransmission is currently suspended in any of the GDF rings 0 through 3,a receipt or transmission, respectively, may be resumed for each‘suspended GDF ring 0 through 3 if the suspended GDF ring 0 through 3 isno longer congested, or full, and no other GDF ring 29 is currentlyreceiving or transmitting a GDF. In another example, the GDF rings 29may be prioritized with respect to one another allowing certain GDFrings 29 to have resume priority over the other GDF rings 29.

FIG. 6 shows an EHWIC GDF. The following are bus codes that may be usedwith regard to the GDF rings (queues) 29:

Command Opcode 0×12: GDFs passed between the EHWIC 10 and the host 14may begin with a 0×12 byte in order to indicate GDF encapsulation. The0×12 Command Opcode may be followed by a GDF queue byte.

GDF Queue: The GDF queue field indicates which GDF queue a correspondingdata frame belongs to, and whether or not the corresponding data frameis a continuation, which may be a resumption of a GDF frame previouslysuspended, such as through a suspend transmit request for GDF queuecontrol byte. The byte encodings are as follows:

Bit 7: Frame Resume Indicator: Indicates whether a GDF frame is acontinuation.

0×0—This is the beginning of a new GDF frame (not previously suspendedby a “Suspend Transmit Request for GDF Queue” control byte, followed by0×F5 “Frame Suspend Indicator”).

0×1—This GDF frame is a continuation (frame previously suspended by a“Suspend Transmit Request for GDF Queue” control byte, followed by 0×F5“Frame Suspend Indicator”).

The Frame Resume Indicator bit may only be used for error detection;e.g. if the host termination logic 20 receives a continuation frame whennew frame is expected, this will be reported as an error event.

Bits 6-2: Unused—Set to zeroes.

Bits 1-0: GDF Queue: Indicates the GDF ring 29 that the correspondingframe belongs to: 0×0—GDF ring 0; 0×1—GDF ring 1; 0×2 GDF ring 2; and0×3—GDF ring 3.

Data: The “Data” field may be any data of any non-zero length (providingof course that it follows the implementation-specific format agreed uponby host driver software and the EHWIC termination logic 24). Forexample, this could be an IP packet, ATM cell, or PPP frame,encapsulated with a port number or VC number in the header.

Rx Flags: For GDFs passed from the EHWIC 10 to the host platform 14, theupper 2 bits of the Rx Flags byte may be written to a receive bufferdescriptor word 1 bits 23-22. This may allow the passing of error Istatus information that may not be readily available for insertion intothe beginning of the GDF, for example line CRC calculations that are notcompleted until the end of the frame arriving at the a physical layerinterface device for data transfer device on the EHWIC 10 that do notstore the entire frame before passing it up to the host.

The Rx Flags byte is also placed into the receive buffer and counted inthe data length field of the receive buffer descriptor, so if the RxFlags functionality is not needed this byte may be used for frame dataas long as the host processor ignores the Rx Flags in the Receive BufferDescriptor (word 1 bits 23-22).

Cyclic redundancy check 8 (CRC8): 8-bit mathematical manner in which tocalculate data for corruption, which may be performed on all frame bytesexcept the CRC8 field itself. Additionally, the CRC8 may not becalculated over any inserted control frames.

Control frames may have three principal functions: 1) flow control bymeans of stop, resume, and transmit control characters, 2) read/writecommands utilized to perform the functions of the legacy parallel port,and, 3) interrupt frames. A control frame (or byte) may be transmittedif and only if the respective control bit (TxCtrl or RxCtrl is “1”). Adata frame may be transmitted if and only if the respective control bit(TxCtrl or RxCtrl) is “0”.

The control frames for implementing the suspend transmit requests andresuming transmit requests for the GDF rings 0 through 3 are below:

0×A0—Suspend Transmit Request for GDF Ring 0: This control character maybe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party suspend transmitting data frames for GDF ring 0.This is intended for flow control purposes, to prevent the overflow of afirst in first out (FIFO) or the GDF ring 0 that is becoming full. Uponreceiving a “suspend transmit” request, a transmitting party may send amaximum of 128 more GDF bytes from GDF ring 0 before ceasingtransmission of all GDF bytes from the GDF ring 0. After this, thetransmitting party may continue transmitting other types of data frames.If the transmitting party is not currently transmitting a GDF from GDFring 0, it may continue transmitting other types of data frames withoutinterruption. However, it may only transmit up to 128 more bytes fromthe GDF ring 0 until such time as it receives a resume byte.

0×A3—Resume Transmit Request for GDF Ring 0: This control character maybe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party resume data frame transmission for GDF ring 0,after transmission has been suspended by the “Suspend Transmit Requestfor GDF Ring 0” control byte.

0×A5—Suspend Transmit Request for GDF Ring 1: This control character maybe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party suspend transmitting data frames for GDF ring 1.This is intended for flow control purposes, to prevent the overflow of aFIFO or GDF ring 1 becoming full. Upon receiving a “suspend transmit”request, the transmitting party may send a maximum of 128 more GDF bytesfrom the GDF ring 1 before ceasing transmission of all GDF bytes fromthe GDF ring 1. After this, the transmitting party may continuetransmitting other types of data frames. If the transmitting party isnot currently transmitting a GDF from GDF ring 1, it may continuetransmitting other types of data frames without interruption. However,it may only transmit up to 128 more bytes from the GDF ring 1 until suchtime as it receives a resume byte.

0×A6—Resume Transmit Request for GDF Ring 1: This control character canbe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party resume data frame transmission for GDF ring 1,after transmission has been suspended by the “Suspend Transmit Requestfor GDF Ring 1” control byte.

0×A9—Suspend Transmit Request for GDF Ring 2: This control character canbe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party suspend transmitting data frames for GDF ring 2.This is intended for flow control purposes, to prevent the overflow of aFIFO or GDF ring 2 that is becoming full. Upon receiving a “suspendtransmit” request, the transmitting party may send a maximum of 128 moreGDF bytes from the GDF ring 2 before ceasing transmission of all GDFbytes from the GDF ring 2. After this, the transmitting party maycontinue transmitting other types of data frames. If the transmittingparty is not currently transmitting a GDF from GDF ring 2, it maycontinue transmitting other types of data frames without interruption.However, it may only transmit up to 128 more bytes the GDF ring 2 untilsuch time as it receives a resume byte.

0×AA—Resume Transmit Request for GDF Ring 2: This control character canbe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party resume data frame transmission for the GDF ring 2,after transmission has been suspended by the “Suspend Transmit Requestfor GDF ring 2” control byte.

0×AC—Suspend Transmit Request for GDF Ring 3: This control character canbe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party suspend transmitting data frames for the GDF ring3. This is intended for flow control purposes, to prevent the overflowof a FIFO or the GDF ring 3 that is becoming full. Upon receiving a“suspend transmit” request, the transmitting party may send a maximum of128 more GDF bytes from the GDF ring 3 before ceasing transmission ofall GDF bytes from the GDF ring 3. After this, the transmitting partymay continue transmitting other types of data frames. If thetransmitting party is not currently transmitting a GDF from the GDF ring3, it may continue transmitting other types of data frames withoutinterruption. However, it may only transmit up to 128 more bytes fromthe GDF ring 3 until such time as it receives a resume byte.

0×AF×Resume Transmit Request for GDF Ring 3: This control character canbe sent either by the host platform 14 or by the EHWIC 10, to requestthat the other party resume data frame transmission for the GDF ring 3,after transmission has been suspended by the “Suspend Transmit Requestfor GDF Ring 3” control byte.

0×F5—Frame Suspend Indicator: This control character may be sent eitherby the host platform or by the EHWIC 10, in response to a GDF QueueSuspend Transmit request, such as that corresponding to control bytes0×A0, 0×A5, 0×A9, or 0×AC, in order to indicate that a current GDF hasbeen suspended and not completely transmitted. This indicates to areceiving party that it has received only a partial frame and it shouldact accordingly (for example, wait for the rest of the frame beforechecking the CRC8 field or forwarding the frame).

The 0×F5 control byte is the end-of-frame indicator for a suspended(partial) frame. After the last byte of the suspended (partial) frame issent, the 0×F5 control byte should appear before any subsequent anend-of-frame I idle control byte. Once a frame has been suspended withthe 0×F5 Frame Suspend Indicator it may be resumed with a Frame ResumeIndicator discussed in regard to FIG. 6.

The 0×F5 Frame Suspend Indicator may not be sent between the 0×12 EHWICGDF opcode and the EHWIC Generic Data Frame Queue Byte (see FIG. 6).This is because before the queue byte is sent, the receiving logiccannot determine which queue to suspend. Frame Suspend Indicators sentbetween the 0×12 EHWIC GDF opcode and the EHWIC GDF Queue Byte should beignored by the receiving logic, and possibly logged as an error.

The host termination logic 20 may only suspend an in-progress frame (viathe 0×F5 control byte) to the EHWIC 10 in response to receiving a GDFQueue Suspend Transmit request of some type (control bytes 0×A0, 0×A5,0×A9, or 0×AC) from the EHWIC 10. However, the EHWIC 10 may use 0×F5 tosuspend a GDF “spontaneously”; that is, without having prior received aGDF Queue Suspend Transmit Request from the host. Regardless of whetherthe EHWIC module chooses to use spontaneous suspend, it may suspend aGDF queue in response to a GDF Queue Suspend Transmit request receivedfrom the host termination logic 20, and remain suspended until itreceives the respective GDF Queue Resume Transmit Request.

The host termination logic 20 is not allowed to spontaneously suspendGDF's, in part because this should never be necessary because the hosttermination logic 20 controls the order in which data arrives from thehost controller (via DMA), and in part in order to keep the EHWIC 10logic unburdened from receiving spontaneously suspended GDF's.

The memory 16 and termination logic 20, 24 is additionally oralternatively a computer readable storage medium with processinginstructions. Data representing instructions executable by theprogrammed CPU 18 and termination logic 20, 24 provided for operating ahost platform-daughtercard configuration. The instructions forimplementing the processes, methods and/or techniques discussed hereinare provided on computer-readable storage media or memories, such as acache, buffer, RAM, removable media, hard drive or other computerreadable storage media. Computer readable storage media include varioustypes of volatile and nonvolatile storage media. The functions, acts ortasks illustrated in the figures or described herein are executed inresponse to one or more sets of instructions stored in or on computerreadable storage media. The functions, acts or tasks are independent ofthe particular type of instructions set, storage media, processor orprocessing strategy and may be performed by software, hardware,integrated circuits, firmware, micro code and the like, operating aloneor in combination. Likewise, processing strategies may includemultiprocessing, multitasking, parallel processing and the like. In oneembodiment, the instructions are stored on a removable media device forreading by local or remote systems. In other embodiments, theinstructions are stored in a remote location for transfer through acomputer network or over telephone lines. In yet other embodiments, theinstructions are stored within a given computer, CPU, GPU, or system.

In one example, the operations of FIGS. 4 and 5 may be performed throughlogic encoded on at least one memory and executed on at least one of theassociated processors as described in regard to FIGS. 1-3. The logic ineach memory is appropriate for the associate processor. Logic encoded inone or more tangible media for execution is defined as the instructionsthat are executable by a programmed processor and that are provided onthe computer-readable storage media, memories, or a combination thereof.

Any of the devices, features, methods, and/or techniques described maybe mixed and matched to create different systems and methodologies.

While the invention has been described above by reference to variousembodiments, it should be understood that many changes and modificationscan be made without departing from the scope of the invention. It istherefore intended that the foregoing detailed description be regardedas illustrative rather than limiting, and that it be understood that itis the following claims, including all equivalents, that are intended todefine the spirit and scope of this invention.

1. An apparatus comprising: a network interface card configured to:generate a plurality of direct memory access (DMA) read requests;transmit at least two of the plurality of DMA read requests over a busto a host without reception of a DMA read response to at least one ofthe plurality of DMA read requests from the host.
 2. The apparatus ofclaim 1, wherein the network interface card is configured to transmitthe at least two of the plurality of DMA read requests over a pluralityof transmissions.
 3. The apparatus of claim 1, wherein the networkinterface card is configured to transmit up to a maximum number of DMAread requests that are allowed to be pending with the host withoutreception of a DMA read response from the host.
 4. The apparatus ofclaim 3, wherein the maximum number of DMA read requests that areallowed to be pending with the host comprises eight DMA read requests.5. The apparatus of claim 1, wherein the network interface card isfurther configured to transmit DMA write frames that are interleavedwith the plurality of DMA read requests.
 6. A system comprising: a hostconfigured to: receive a plurality of direct memory access (DMA) readrequests over a bus from a network interface card; generate a DMA readresponse to at least one of the plurality of DMA read requests afterreceipt of at least two of the plurality of DMA read requests.
 7. Thesystem of claim 6, wherein the host is configured to receive the atleast two of the plurality of DMA read requests over a plurality oftransmissions.
 8. The system of claim 6, wherein the host is configuredto receive a maximum number of DMA read requests that are allowed to bepending with the host prior to generation of a DMA read response to atleast one of the plurality of DMA read requests.
 9. The system of claim8, wherein the maximum number of DMA read requests that are allowed tobe pending with the host prior to generation a DMA read responsecomprises eight DMA read requests.
 10. The system of claim 6, whereinthe host is configured to transmit a plurality of DMA read responses tothe plurality of DMA read requests in an order corresponding to an orderthat the host received the plurality of DMA read requests.
 11. Thesystem of claim 6, further comprising the network interface card incommunication with the host through the bus, wherein the networkinterface card is configured to: generate the plurality of DMA readrequests; and transmit at least two of the plurality of DMA readrequests over the bus to the host without reception of a DMA readresponse from the host.
 12. The system of claim 11, wherein the networkinterface card is further configured to transmit the plurality of DMAread requests interleaved with DMA write frames.
 13. A methodcomprising: generating, with a network interface card, a plurality ofdirect memory access (DMA) read requests; and transmitting, with thenetwork interface card, at least two of the plurality of DMA readrequests over a bus to a host without receiving a DMA read response fromthe host.
 14. The method of claim 13, wherein transmitting, with thenetwork interface card, at least two of the plurality of DMA readrequests comprises: transmitting, with the network interface card, atleast two of the plurality of DMA read requests in a plurality oftransmissions.
 15. The method of claim 13, wherein transmitting, withthe network interface card, at least two of the plurality of DMA readrequests comprises transmitting, with the network interface card, up toa maximum number of DMA read requests that are allowed to be pendingwith the host.
 16. The method of claim 15, wherein the maximum number ofDMA read requests that are allowed to be pending with the host compriseseight DMA read requests.
 17. The method of claim 13, further comprising:interleaving, with the network interface card, a plurality of DMA writeframes with the plurality of DMA read requests; and transmitting, withthe network interface card, the plurality of DMA write framesinterleaved with the plurality of DMA read requests.
 18. The method ofclaim 13, further comprising: receiving, with the host, at least two ofthe plurality of DMA read requests over the bus from the networkinterface card; and generating, with the host, a DMA read response to atleast one of the plurality of the plurality of DMA read requests afterreceiving the at least two of the plurality of DMA read requests. 19.The method of claim 18, wherein receiving, with the host, at least twoof the plurality of DMA read requests over the bus from the networkinterface card comprises: receiving, with the host, a maximum number ofDMA read requests that are allowed to be pending with the host; andwherein generating, with the host, a DMA read response to at least oneof the plurality of DMA read requests comprises: generating, with thehost, a plurality of DMA read responses to the plurality of DMA readrequests after receiving the maximum number of DMA read requests. 20.The method of claim 19, further comprising: transmitting, with the host,the plurality of DMA read responses in an order corresponding to anorder in which the DMA read requests were transmitted.